This invention relates to clock systems for control of computers or other electronic circuits, and in particular to a method for generating and distributing clock signals corresponding to phases of a master clock.
In the manufacture of computer systems and other circuits, clock signals are often provided to various elements such as components or circuits, on a single chip, or to elements scattered throughout the computer system itself. For a complex network of data communication paths, such as found in a conventional computer system, whether distributed on a single chip or over several chips, many clock signals must occur at times precisely related to the clock signals of adjacent parts of the system. In such a system, "adjacent" can mean parts of the circuit which are disposed relatively far away from one another but are adjacent in an electronic timing sense. As computer systems have evolved to operate at higher and higher clock speeds, the design and debugging of such clock distribution systems has become an extraordinarily difficult task.
In typical prior art computer systems, a master clock signal is generated for, or otherwise supplied to, a chip or printed circuit board. The clock signal is then distributed using conductive lines throughout the circuit. The designer of such a system must take great care to ensure that the clock signal arrives at an appropriate time at each of the circuits it controls. This is time consuming and expensive.
Typical prior art clock distribution systems are described in: Bakoglu, H. B., Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley (1990); Glasser, Lance A., et al., The Design and Analysis of VLSI Circuits,Addison-Wesley (1985); Rettberg, Randall D., et al., U.S. Pat. No. 4,700,347, entitled "Digital Phase Adjustment" (October 1985); Eby Friedman, "Clock Distribution, " IEEE Press (1993); and Weste & Eschraghian, Principles of CMOS VLSI Design, 2nd edition, Addison-Wesley (1993).